DeFT Semiconductors Joins Forces with Leading Fabless Companies

The semiconductor industry is undergoing a massive transformation. With Moore's Law slowing, design complexity exploding, and time-to-market windows shrinking, innovation in silicon design and test is more important than ever. To stay ahead of the curve, strategic partnerships are no longer optional—they’re essential. That’s why we’re thrilled to announce a major milestone: DeFT Semiconductors has officially joined forces with several leading fabless semiconductor companies across the globe.

This collaboration marks a bold new chapter in how DFT (Design-for-Test) is integrated, executed, and optimized at scale. By working hand-in-hand with top-tier design houses, DeFT is helping redefine what’s possible in test architecture, yield optimization, and next-generation SoC reliability. In this article, we’ll unpack what this partnership means for the industry, how it benefits our clients, and what the future holds.

1. The Fabless Model: Speed Meets Innovation

Fabless semiconductor companies focus entirely on chip design, outsourcing manufacturing to foundries like TSMC, Samsung, or GlobalFoundries. This model enables rapid innovation without the enormous costs of running fabrication facilities.

However, the fabless model comes with unique challenges—especially in the realm of test. These companies need robust, scalable, and efficient DFT solutions that work seamlessly across multiple foundries and process nodes. DeFT’s expertise in cross-foundry DFT implementation makes us the perfect partner for fabless leaders pushing the envelope in AI, 5G, automotive, and IoT.

2. A Collaborative Approach to SoC Test Complexity

Today’s SoCs (System-on-Chip) are more like systems-in-a-box, combining CPUs, GPUs, NPUs, high-speed interfaces, security modules, and massive amounts of embedded memory—all within a single silicon die or chiplet stack.

DeFT’s partnership with fabless firms enables deeper integration at the architectural level. We collaborate during early RTL and floorplanning stages to co-design test strategies that ensure:

• Full test coverage of internal and external interfaces

• Minimal area and performance impact

• Hierarchical scan and compression tailored for SoC partitioning

• Seamless integration of third-party IP DFT logic

This close coordination ensures that test isn’t a bottleneck—it’s a launchpad for faster validation and time-to-market.

3. Accelerating Tape-Outs with Pre-Verified DFT IP

To meet tight development cycles, fabless companies need DFT flows that are plug-and-play, reusable, and silicon-proven. That’s exactly what DeFT delivers through our library of pre-verified DFT IP blocks, including:

• Configurable scan wrappers

• Test controllers for hierarchical test

• Memory BIST generators

• Logic BIST modules

• Secure boundary scan interfaces

By integrating these IPs early, fabless teams can shave weeks off their DFT implementation time and gain confidence that test logic will work flawlessly in first silicon.

4. Cross-Foundry Compatibility & Optimization

Each foundry has its own PDKs (process design kits), DRC rules, and test infrastructure requirements. Navigating this variability is one of the hardest parts of scaling DFT across product lines. DeFT bridges this gap.

We’ve engineered our DFT flows to be foundry-agnostic but fully customizable to each fab’s test infrastructure. This means fabless customers can confidently tape out to multiple foundries without redoing their test logic—whether they’re on TSMC N3, Samsung 4LPP, or GlobalFoundries 22FDX.

By ensuring compatibility and compliance with foundry-specific DFT guidelines, we reduce risk, accelerate production, and improve yield across the board.

5. Integrated Analytics for Yield and Reliability

Once silicon is in hand, post-production testing and analytics become the keys to maximizing profitability. DeFT enables fabless companies to get the most from their test data through integrated yield analytics, fault classification, and root-cause detection.

We provide infrastructure for:

• Real-time logging of test results

• Fail signature clustering using AI

• Yield dashboards for fab teams

• Feedback loops to improve ATPG and DFT coverage

This data-driven approach not only improves yield over time but also helps fabless companies identify reliability concerns early—before they hit the market.

6. Supporting Chiplet and 3D IC Strategies

Many fabless innovators are betting big on chiplets and 3D stacking. These architectures offer modularity, cost-efficiency, and performance scaling beyond traditional monolithic chips. But they also introduce enormous DFT complexity.

DeFT has developed custom solutions to support these emerging needs, including:

• Pre-bond and post-bond DFT structures

• Die-to-die interface test logic

• Modular scan partitioning for chiplets

• Shared BIST engines for stacked dies

By working alongside fabless chiplet developers, we’re pioneering test strategies for the future of heterogeneous integration.

7. Trusted by Industry Leaders

We’re proud to be working with some of the most respected names in the fabless ecosystem, from AI startups developing bleeding-edge accelerators to established names delivering next-gen mobile SoCs. While confidentiality prevents us from naming them all, we can confidently say that these companies chose DeFT because of:

• Proven silicon success

• Industry-compliant flows

• Responsive engineering support

• Future-ready DFT innovation

Our joint successes are already yielding higher first-silicon pass rates, lower test costs, and faster ramp-ups—proving the power of true collaboration.

8. Looking Ahead: The Road to 2nm and Beyond

As the industry marches toward 2nm, the demands on DFT will only intensify. At these scales, atomic-level defects, quantum effects, and power density will push current test strategies to their limits. DeFT is already preparing for this next wave.

We’re investing in:

• Machine learning-driven ATPG

• Adaptive BIST with in-field telemetry

• Secure, on-die diagnostics

• High-speed, compressed test access for chiplet fabrics

By continuing to partner with fabless leaders, we aim to co-create the next generation of silicon—not just functional, but self-aware, self-healing, and test-ready from day one.

Conclusion

DeFT Semiconductors' alliance with leading fabless companies is more than a partnership—it's a strategic collaboration to push the boundaries of what’s possible in chip design and test. Together, we're not just solving today’s challenges; we’re shaping the future of silicon innovation.

From test IP integration and hierarchical scan design to 3D IC enablement and AI-based diagnostics, DeFT is powering the testability of the world’s most advanced chips. We’re honored to be the DFT partner of choice for industry pioneers—and we’re just getting started.

FAQs

1. Why are fabless companies partnering with DeFT Semiconductors?Because DeFT offers end-to-end DFT expertise, silicon-proven IP, and scalable test solutions tailored for the fast-moving fabless model. Our flows reduce risk, improve test coverage, and accelerate tape-outs across foundries.

2. What kind of chips does DeFT support with its DFT solutions?We support a wide range—from mobile SoCs and AI accelerators to automotive controllers, chiplets, and 3D ICs. Our modular DFT infrastructure scales from low-power edge chips to high-performance processors.

3. How does DeFT handle cross-foundry DFT implementation?Our DFT flows are built to be foundry-agnostic but easily configurable to meet specific foundry requirements. We maintain close relationships with TSMC, Samsung, and GlobalFoundries to ensure compliance.

4. Does DeFT help with post-silicon analytics too?Yes. We provide tools and infrastructure for collecting, analyzing, and visualizing post-silicon test data. This helps fabless companies boost yield, debug faster, and continuously refine their test strategies.

5. Is DeFT prepared for future nodes like 2nm?Absolutely. We're investing in AI-powered ATPG, in-field diagnostics, and scalable test access technologies to support future process nodes, chiplet fabrics, and quantum-aware architectures.